Board-on-chip (“BOC”) techniques have been used for packaging high speed memory components. FIG. 1A is a cross-sectional view of a BOC semiconductor assembly in accordance with the prior art. As shown in FIG. 1A, the semiconductor assembly 100 includes a substrate 102, a semiconductor die 104 attached to the substrate 102 with an adhesive 106, and an encapsulant 108 encapsulating the semiconductor die 104 and at least a portion of the substrate 102. The substrate 102 includes a first side 102a proximate the semiconductor die 104, a second side 102b opposite the first side 102a, and an opening 118 between the first and second sides 102a and 102b. The opening 118 exposes a connection region 110 on the semiconductor die 104. A plurality of traces 112 are located on the second side 102b of the substrate 102 and are electrically connected to the connection region 110 via a plurality of wirebonds 114. A plurality of electrical couplers 116 (e.g., solder balls) are attached to ball sites on the substrate 102.
FIG. 1B is a bottom view of the semiconductor assembly 100 of FIG. 1A, and FIG. 1C is an enlarged view of a portion of the semiconductor assembly 100 shown in FIG. 1B. As shown in FIGS. 1B and 1C, the semiconductor die 104 can include a plurality of bond sites 119 in the connection region 110. The individual bond sites 119 are coupled to corresponding terminals 113 of the individual traces 112 on the semiconductor substrate 102 via the wirebonds 114. As is clearly shown in FIGS. 1B and 1C, the plurality of traces 112 fan out from the terminals 113 to contact corresponding ball pads 120.
Over the course of time, manufacturers have made dies smaller and smaller to meet user demands. As the semiconductor dies 104 have become smaller, the number of ball pads 120 and the traces 112 required on the substrate 102 has increased such that the large ball pads 120 can interfere with routes of the traces 112. One conventional solution for dealing with this problem is to use aggressive design rules and wire bond profiles to decrease the sizes of all features on both the semiconductor die 102 and the substrate 104. However, such a conventional technique is still limited due to the number of ball pads 120 that are typically required.